Conventional computer systems generally include a central processing unit (“CPU”) providing primary control of the computer system. The CPU is connected through a host bus to a Host/PCI (e.g., Peripheral Component Interconnect) bus bridge. The Host/PCI bus bridge is connected to a PCI bus, which is connected to peripheral components such as local area networks, graphics cards, and mass media devices. The Host/PCI bus bridge interfaces among the CPU, the main memory, and the peripheral components.
Different bus architectures abound in the current state of computer technology. An example of a modern bus is the PCI bus. The PCI bus is a high performance, low latency system bus, generally defined by the PCI Special Interest Group (“SIG”) in PCI Local Bus Specification, Revision 2.3 (released Mar. 20, 2002). The PCI bus will be used to illustrate some of the principles behind and operation of the various embodiments disclosed herein. However, those principles may also be applied to other bus architectures.
When a device is connected to a PCI bus, an amount of memory is allocated to (e.g., reserved for) the device, if necessary. The manufacturer of the device generally sets the amount of memory to be allocated to the device, which is currently based on the number of read-only bits in a base address register (“BAR”) associated with the device. In a typical system, the number of read-only bits is hardwired and cannot be altered.
In order to determine the number of read-only bits in the BAR, the BIOS (e.g., basic input/output system) or other software writes a series of all 1's to the BAR and then reads the resultant BAR. When the resultant BAR is read, the read-only bits return a value of 0 (e.g., usually a series of 0's in the lower bits of the relevant field of the BAR). The BIOS can then allocate memory to the device based on the number of read-only bits in the BAR.
In systems that employ a PCI bus, the amount of memory to be allocated to each device is set during enumeration, which is the procedure used by software (e.g., generally the BIOS or Operating System) to determine which devices are connected to the PCI bus and how much memory each device requires. Generally, the default amount of memory indicated as necessary by the BAR is equal to the largest possible amount of memory that the device can consume during operation. The default setting for some devices can be large, which is problematic if the device actually requires less than the entire allocated amount of memory.
In instances where the device does not require all of the allocated memory, a memory hole may be created such that a certain amount of memory space is unused. Naturally, unused memory reduces the efficiency and overall throughput of the system.
Besides allocating the largest possible amount of memory space to a device, another solution is to allow the device to calculate the amount of memory required by the device and configure the number of read-only bits in the BAR accordingly. However, this requires additional logic or pins and places a burden on devices that require variable amounts of memory to have information readily available regarding the quantity and size of all devices coupled to the bus before enumeration.